Assistant Professor, Electrical Communication Engineering
|Contact||(+91) 80-2293 2656 (+91) 80-2360 0563 firstname.lastname@example.org|
|Interests||Computational Electromagnetics, High-speed Circuits, Cloud Computing|
University of Washington, Seattle, 2003, MS
Indian Institute of Technology, Kharagpur, 2000, BTech
|Biosketch||Areas of Interest||Teaching||Services and Awards||Publications|
Dipanjan Gope, PhD, is Assistant Professor in Electrical Communication Engineering at Indian Institute of Science, Bangalore. He is also co-founder and CEO at Simyog Technology Pvt. Ltd. a spin-off from IISc focused on Design and Sign-off tools for Automotive Electronics. His research interests include computational electromagnetics with applications in signal integrity, power integrity, EMI for high speed chip-package-systems, RF sensing for IoT applications, parallel programming for many-core and cloud infrastructures. Dr. Gope is a founding member at Nimbic (acquired by Mentor Graphics) where he served as Vice President, R&D from 2007-2011 and 2013-2014. Between 2005-2007, he was a Senior CAD engineer at Intel where he was a recipient of a divisional award for contributions towards providing signal integrity solution to Intel architecture platforms. As part of his PhD dissertation, he co-developed the PILOT technology for fast circuit-electromagnetic simulation, now licensed by the University of Washington. He has more than 60 journal and conference publications. Dr. Gope received his PhD and M.S. degrees in Electrical Engineering from the University of Washington, Seattle and BTech in Electronics and Electrical Communication Engineering from the Indian Institute of Technology, Kharagpur.
The solution of Maxwell’s equations for irregular 3D structures have been used traditionally for oil-exploration, detection of radar-cross-section of military vehicles, antenna analysis, bio-medical applications and more recently in predicting electrical performance of RF and high speed circuits and systems. Since 1950s applied mathematics, physics, and engineering communities have refined the EM solution using 3 fundamental analysis techniques: Finite Element Method (FEM), Finite Difference Time Domain (FDTD) method and the Method of Moments (MoM) or the Boundary Element Method (BEM). The accuracy of simulated results and the time and memory requirements are key indicators of any solution methodology. While the community has successfully addressed many challenges over the last few decades, several problems including fast direct solvers, effective full-wave preconditioners, incremental or design specific solvers remain unsolved or partially solved.
With the increasing bit rates for communication, chip-package-system level challenges like signal integrity (SI), power integrity (PI) and electromagnetic interference (EMI) play a crucial role in circuit design. RLGC parasitics or S-parameter extraction tools have been used for modeling the electromagnetic behavior of on-chip inductors and package-board interconnects using different flavors of solution methodology: 2D, 2.5D, 3D. The move towards low-cost packages with minimum layer-count, ground planes with holes, and 3D die-stacking renders a 3D treatment necessary for critical regions for accurate modeling. Therefore, the complexity of analyzing large structures like complete package and board systems with 3D accuracy presents a time and memory bottleneck. The fast solver algorithms of the last two decades have alleviated the problem at the verification stage, but the quick turn-around time required for design has been elusive. Automatic hybrid 3D-2.5D-2D formulations aided by pattern recognition may provide the incentive required for a wide-spread use of 3D tools in the design stages.
The BEM technique uses a surface or interface mesh and gives rise to a smaller matrix size but in dense form which presents a time and memory bottleneck. In the last two decades several fast iterative solver algorithms have been devised to mitigate the problem, namely, Fast Multipole Method (FMM), low-rank based methods and Pre-corrected FFT based method. While these algorithms are capable of reducing the cost of matrix-vector products to O(N) or O(NlogN), the solution time is impeded by the convergence rate of the iterative solution and will require better pre-conditioning techniques particularly for full-wave applications. For the solution of very large number of right-hand-side (RHS), a different iteration-free variant of fast solvers or in other words, fast direct solvers can be very effective in expediting the matrix solution. The challenges involve reducing a traditionally O(N3) LU decomposition process to a faster linear complexity method exploiting the underlying physics of the interactions between basis functions.
RF or microwave imaging techniques, due to its non-invasive, non-ionizing, low-power and low-cost features, is amenable to regular monitoring of some diseases like breast cancer, towards early detection or post-treatment tracking. The benign-adipose and cancerous tissues exhibit different material properties, namely permittivity and conductivity in the frequency range of 100MHz to 20GHz. Given an electromagnetic field excitation, this results in different scattered fields from healthy and diseased tissues, which can be used to detect and monitor breast health. Over the last couple of decades several full-wave image reconstruction algorithms have been proposed. However, a commercial solution towards RF imaging for breast cancer detection is yet to materialize. The reason can be attributed to the computational challenges involved in the ill-posed, non-linear, inverse solution of 3D full-wave Maxwell’s equations which is further exacerbated by the presence of benign fibro-glandular tissue that demonstrate low dielectric contrast with malignant tissue in the RF spectrum. The emergence of cloud computing, prominence of internet connected devices and the advances in optimization and machine learning approaches present a unique opportunity to usher in a new paradigm of personalized RF imaging sensor devices.
Antennas constitute the receiver and transmitter ends for wireless communication channels. With the recent deluge in the use of mobile phones, wearable devices and in general wireless transmission, a plethora of antenna types have come to the forefront with different characteristics and application areas. The antenna properties like gain, directivity and efficiency are also dependent on the mounting structure e.g. the vehicle for military vehicular antennas and the package-board-heat-sink-chassis for those in microelectronic systems. While the field of antenna analysis is fast gaining maturity, the area of effective antenna design or synthesis tools, particularly in the presence of mounting structures, is still at a nascent stage. Although, theoretically the design problem stands to benefit from advances in the forward analysis methodology, in reality several gaps in theory, algorithms and implementation need to be addressed before design and synthesis tools can be developed to effectively serve as suitable aid to engineers.
A right hand shift in the power-constrained commodity microprocessor roadmap has given rise to the many-core CPU architectures that rely on increasing the number of cores rather than clock frequency to deliver increased computing performance. Therefore, algorithms with non-trivial serial content will not scale in terms of efficiency in accordance to Amdahl’s law. Consequently, fast solver algorithms of the next generation need to be amenable to parallelization and implemented with appropriate load-balancing, synchronization and cache utilization. The emergence of cloud computing and the corresponding on-demand availability of custom computing instances, also present a unique opportunity to meet the time-memory requirements and enter the magical “simulation-in-a-coffee-break” paradigm. Further, the main-streaming of GPU and FPGA processors and the increasing bus-speeds for CPU communication, may provide avenues for unprecedented speedup and memory capacity.
E8 262: CAD for High Speed Chip-Package-Systems
E0 245: Android Sensor Programming
- 2017: Visvesvaraya Young Faculty Resarch Fellow, Ministry of Electronics and Information Technology
- 2013: Department of Science and Technology (DST) Young Scientist Fasttrack (Engineering Sciences)
- 2012: IEEE Senior Member
- 2006: Divisional Recognition Award for delivering signal integrity analysis for Intel architecture platforms
- 2003: Co-author, "Best Paper in Session" (Mixed Signal Technology) SRC Techcon03
- 2015: Ms. Nikita Ambasana, Student Software Demonstration Prize, IEEE EPEPS 2015, San Jose, CA, USA
- 2015: Mr. Arkaprovo Das, Best paper in session award (Communications), EECS, IISc 2015, Bangalore, India
- 2014: Ms. Nikita Ambasana, Best student paper award, IEEE EDAPS 2014, Bangalore, India
- 2015-Present: Technical Program Committee member, IEEE SPI
- 2015-Present: Technical Program Committee member, IEEE EPEPS
- 2015-Present: International Steering Committee Member, IEEE EDAPS
- 2014: General Co-chair, IEEE EDAPS
- 2014: Technical Program Committee member, IEEE DAC
- 2014: Technical Program Committee member, IEEE DATE
- 2014-2015: Technical Program Committee member, IEEE ASP-DAC
- 2012: Track Chair, "Interconnect and Power Networks", IEEE ICCAD
- 2011: Panelist, "Parallel or Paralyzing: Is parallel EDA worth the trouble", IEEE DAC
- 2011: Panelist, "Cloud computing for electronic co-design", DesignCon
- 2010-2012: Technical Program Committee member, IEEE ICCAD
- 2010: Tutorial "Navigating electromagnetic field solvers: Designer and EDA perspectives," Designcon
- 2008-2011: Affiliate faculty in Electrical Engineering, University of Washington
- 2006: Co-Chair, "Parasitic Simulation and Modeling" in IEEE ICCAD
- 2005: Co-Chair, "Advances in Fast Algorithms for Integral Equations" in IEEE APS-URSI
- 2005: Co-chair, "Extraction and Modeling for Interconnect Structures" in IEEE ICCAD